Diffusion of dopant atoms and other atoms in integrated circuit (IC) structures is responsible for a number of problems associated with the fabrication and long term stability of IC structures. For example, electrical characteristics of static random access memory (SRAM) structures are adversely affected by lateral diffusion in polysilicon of dopant such as phosphorus from strongly n+ doped regions. This causes N+/P+ junctions between NFET and PFET devices to shift towards the PFET device.
In order to ameliorate the problem, a shallower n+ pre-doped implant and a smaller N+ implanted area have been adopted. However, substantial diffusion of dopant still occurs during subsequent thermal processing such as polysilicon reoxidation processes and rapid thermal annealing (RTA).
Furthermore, diffusion of extrinsic dopant and source/drain dopant into the channel region can occur, again resulting in an adverse effect on electrical characteristics of the structure. For example, the threshold voltage at which a channel region of a transistor device begins to conduct typically reduces with increased amounts of lateral diffusion of extrinsic and source/drain dopant. Consequently, sub-threshold leakage can be increased by several orders of magnitude.
To mitigate this problem, a reduced dose of dopant may be applied when forming a halo region, and a lower temperature employed in the course of rapid thermal annealing of the structure. However, such measures may introduce further problems such as gate induced drain leakage (GIDL) and a lack of dopant activation.